1. Technical Field of the Invention
This invention relates generally to digital circuitry and more particularly to phase locked loops.
2. Description of Related Art
Phase locked loops (PLLs) are known and widely used to generate a reliable clock signal. In general, an analog PLL includes a phase and/or frequency detector, a charge pump, a loop filter, a voltage controlled oscillator (VOC), and a feedback divider. The phase and/or frequency detector detects a phase and/or frequency difference between a reference oscillation (usually provided by a crystal oscillator circuit) and a feedback oscillation to produce an up signal when the feedback oscillation lags behind the reference oscillation, a down signal when the feedback oscillation leads the reference oscillation, or a neutral signal.
The charge pump converts the up signal into an up current, the down signal into a down current, and the neutral signal into a neutral current. The loops filter converts the currents into a control voltage that is provided to the VCO. The VCO generates an output oscillation based on the control voltage. The feedback divider divides the output oscillation by a divider value to produce the feedback oscillation. Note that the rate of the output oscillation (fOUT) is dependent upon the divider value (N) times the rate of the reference oscillation (fIN), where fOUT=N*fIN.
When the desired rate between the output oscillation and the reference oscillation is an integer, the design of the feedback divider is relatively simple and straightforward. When the desired rate between the output oscillation and the reference oscillation is not an integer, there are several ways to achieve a fractional divider value. One technique is to divide the reference oscillation by M prior to the phase and/or frequency detector. This provides an output oscillation rate of N/M*fIN. Another technique is to use a fractional-N divider that causes the divider value to bounce back and forth between N and N+1 at a controlled rate to achieve a relative divider value of N.fff, where the “fff” corresponds to a fractional value.
An issue with the fractional-N PLLs is the jitter caused by the constant switching between the two divider values N and N+1. To minimize the adverse affects of the jitter, the overall bandwidth of the PLL is reduced such that as much jitter energy as possible is filtered out by the PLL. However, a narrow bandwidth PLL is susceptible to internally generated noise, which can be filtered out by a wide bandwidth PLL. Thus, the designer must choose between tradeoff a wideband PLL for fractional N divider. This situation makes a low jitter fractional N PLL difficult to design.
Therefore, a need exists for an improved PLL that simultaneously provides a wide bandwidth to reduce internally generated jitter while implementing a fractional-N divider in a low jitter architecture.